1. Field of the Invention
Generally, the present disclosure relates to the manufacturing of integrated circuits, and, in particular, to the creation of photomasks for use in photolithographic processes.
2. Description of the Related Art
Integrated circuits typically include a large number of circuit elements which include, in particular, field effect transistors. Other types of circuit elements which may be present in integrated circuits include capacitors, diodes and resistors. The circuit elements in an integrated circuit may be electrically connected by means of electrically conductive metal lines formed in a dielectric material, for example by means of damascene techniques. The electrically conductive metal lines may be provided in a plurality of interconnect layers that are stacked on top of each other above a substrate in and on which the circuit elements are formed. Metal lines in different interconnect layers may be electrically connected with each other by means of contact vias that are filled with metal.
Due to the complexity of modern integrated circuits, in the design of integrated circuits, automated design techniques are typically employed.
The design of an integrated circuit can employ a number of steps. These steps may include the creation of a user specification that defines the functionality of the integrated circuit. The user specification may be the basis for the creation of a register transfer level description that models the integrated circuit in terms of a flow of signals between hardware registers and logical operations performed on those signals. The register transfer level description of the integrated circuit can then be used for the physical design of the integrated circuit, wherein a layout of the integrated circuit is created. The thus-created layout may be the basis for the formation of photomasks that may be employed for patterning materials in the manufacturing of the integrated circuit by means of photolithography processes.
In a photolithography process, a photomask is projected to a layer of a photoresist that is provided over a semiconductor structure. Portions of the photoresist are irradiated with radiation that is used for projecting the photomask to the photoresist. Other portions of the photoresist are not irradiated, wherein the pattern of irradiated portions of the photoresist and portions of the photoresist that are not irradiated depends on a pattern of printing features provided on the photomask.
Thereafter, the photoresist can be developed. Depending on whether a negative or a positive photoresist is used, in the development process, either the non-irradiated portions or the irradiated portions of the photoresist are dissolved in a developer and, thus, removed from the semiconductor structure.
Thereafter, processes for patterning the semiconductor structure, which, in particular, may include one or more etch processes, may be performed, using the portions of the photoresist remaining on the semiconductor structure as a photoresist mask. Thus, features in accordance with the created layout of the integrated circuit may be formed on the semiconductor structure.
In the formation of small features in semiconductor structures, resolution enhancement techniques may be employed, wherein so-called sub-resolution assist features (SRAFs) are provided on a photomask, in addition to printing features which are employed for forming photoresist features. SRAFs may be provided in the form of small features which may, for example, have a bar shape and which are provided on the photomask in the vicinity of the printing features. When the photomask is used in a photolithography process, typically no features corresponding to the SRAFs are formed in the photoresist mask that is provided on the semiconductor structure. However, the presence of SRAFs can reduce a sensitivity of the photolithography process with respect to variations of parameters of the photolithography process, which may include, in particular, a focus of the projection and a dose of the radiation used for projecting the photomask to the photoresist.
Techniques for placing SRAFs in the layout of a photomask include rule-based SRAF generation methods. Rule-based SRAF generation methods can be fast, in terms of a computation time required for determining the placement of SRAFs, but they are typically not generic and can require significant engineering efforts to set up and maintain a set of rules, which are denoted as “recipes.” Other techniques for SRAF placement include model-based methods, which can provide a higher SRAF quality at a lower recipe complexity. However, model-based methods typically require a longer run time of algorithms employed for the placement of SRAFs.
Model-based methods for SRAF placement can be split into major groups. In a first group of methods, an aerial image simulation with further processing to seed a growth and/or an insertion of manufacturable SRAFs can be employed. In a second group of methods, exact mask layout solutions can be determined by means of inverse lithographic technology, where mask shapes are generated from a target photoresist pattern through an optimization of a pixel-based function over a whole area on the basis of a model representing the photolithography system from the radiation source to the photoresist. The mask solutions given by the inverse lithographic technology can then be converted to SRAF shapes according to mask rule check constraints provided by a photomask manufacturer.
U.S. Pat. No. 8,732,625 discloses methods for creating model-based SRAFs. An SRAF guidance map is created, wherein each design target edge location votes for a given field point on whether a single-pixel SRAF placed on this field point would improve or degrade the aerial image over the process window. The SRAF guidance map can be used to determine SRAF placement rules and/or to fine-tune already-placed SRAFs.
U.S. Pat. No. 8,037,429 discloses a system for producing mask layout data that retrieves target layout data defining a pattern of features, or a portion thereof, and an optimized mask layout pattern that includes a number of printing and non-printing features. Mask layout data for one or more SRAFs is then defined to approximate one or more non-printing features of the optimized mask layout pattern.
Jayaram et al., “Model-based SRAF Solutions for Advanced Technology Nodes,” 29th European Mask and Lithography Conference. Proc. of SPIE Vol. 8886, 88860P, 2013, discloses model-based SRAF placement techniques.
Villaret et al., “Inverse Lithography Technique for advanced CMOS Nodes,” Optical Microlithography XXVI, Proc. of SPIE Vol. 8683, 86830E, 2013, discloses inverse lithography techniques.
While inverse lithography techniques can provide a higher quality of SRAF placement than other known model-based techniques or rule-based techniques for SRAF placement, it can require a relatively large amount of computing time, which can limit the applicability of inverse lithography techniques to the placement of SRAFs in small portions of a photomask that include only a small fraction of the printing features employed in the formation of a photomask for a full chip.
In view of the above-described situation, the present disclosure provides methods, computer readable storage media and computer systems which can provide a high quality of SRAF placement while being fast enough to be used for full-chip runs.